Digital processing devices generally utilise FSM circuits where sequential control is required. A typical synchronous FSM circuit consists of several flip-flops which function to hold the previous state, and several decoding logic gates which function to determine the present state. The output state signal from such an FSM circuit is dependent upon both the previous and present state at the time the flip-flops are clocked. Such a known ‘hard-wired’ FSM circuit is limited in the range of functions that can be performed because the control function of the FSM is fixed, i.e. each time the circuit in a particular state receives a certain input, then the output state signal will be the same.
In order to enable an FSM to perform a greater range of functions, it is known in the art to implement an FSM as a set of instructions for a microprocessor. FIG. 1 illustrates a known programmable FSM circuit 10 comprising a programmable logical array (PLA) 12 as the basic logical element. A first input to the PLA 12 is an external input line 14 and a second input to the PLA 12 is the state register output line 16. A first output from the PLA 12 is an output line 18 and a second output from the PLA 12 is a state register input line 20. The state register 22 has a single output line 24 which divides in two routes, a first route 26 is coupled to another part of the system of which the FSM is a sub-section and a second route is the state register output line 16.
In operation, an input signal on the external input line 14 is fed into the PLA 12 and the state is input to the state register 22 on the state register input line 20. This state is temporarily stored in the state register 22. When a new clock cycle commences, the PLA 12 receives two inputs, a further input signal on the external input line 14 and the state signal representing the previous state of the FSM from the state register output line 16. The PLA acts on these inputs and outputs a data signal to the output line 18 and the state register input line 20.
U.S. Pat. No. 4,675,556 discloses an example of a programmable FSM circuit which utilises a PLA as the basic logical element. The decoding of input signals and state signals is performed using a table of values stored in a memory in the microprocessor. However, the use of a microprocessor to implement an FSM results in higher power consumption than a hard-wired FSM.
U.S. Pat. No. 5,584,021 describes a programmer, which utilises a memory (for example a RAM) as the basic logical element. The programmer changes state during time intervals, and the memory has a start location containing a start time interval for an output signal and an end location containing an end time interval for the output signal, and further comprises means for reading the values in the locations, and a controller for determining the operation of the means for reading the values.